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DATA SHEET
MOS INTEGRATED CIRCUIT
PD78P4916
16-BIT SINGLE-CHIP MICROCONTROLLER
The PD78P4916 is one of the PD784915 subseries in the 78K/IV Series microcontrollers which incorporate a high-speed and high-performance 16-bit CPU. The PD78P4916 replaces mask ROM with one-time PROM and increases on-chip ROM and RAM capacity compared to the PD784915. It is suitable for evaluation at system development and for small quantity production. Detailed descriptions of functions are provided in the following user's manuals. Be sure to read these documents when designing.
PD784915 Subseries User's Manual - Hardware : U10444E
78K/IV Series User's Manual - Instruction : U10905E
FEATURES
High-speed instruction execution using 16-bit CPU core * Minimum instruction execution time: 250 ns (at 8-MHz internal clock) On-chip high capacity memory * PROM : 62 Kbytes Note * RAM Note : 2048 bytes Note
It is possible to change the capacity of the internal PROM and the internal RAM by specifying the internal memory capacity select (IMS) register.
ORDERING INFORMATION
Part Number Package 100-pin plastic QFP (14 x 20 mm)
PD78P4916GF-3BA
The information in this document is subject to change without notice. Document No. U11045EJ1V0DS00 (1st edition) Date Published April 1996 P Printed in Japan
The mark
* shows major revised points.
(c)
1996
PD78P4916
78K/IV Series Products
78K/IV Series
PD784915 mPD784915 Subseries Subseries
78K/I Series
High-performance 16-bit CPU core High-speed operation On-chip analog circuit for VCR
PD78148 Subseries PD78138 Subseries
Enhanced peripheral hardware
2
PD78P4916
Function List (1/2)
Item Internal PROM capacity Internal RAM capacity Operation clock 62 Kbytes
Note
Function
2048 bytes Note 16 MHz (Internal clock: 8 MHz) Low frequency oscillation mode: 8 MHz (Internal clock: 8 MHz) Low power consumption mode: 32.768 kHz (Subsystem clock) 250 ns (at 8-MHz internal clock) Total: 54 Input: 8 I/O: 46
Minimum instruction execution time I/O ports
Real-time output port
11 (including 3 outputs each for Pseudo-VSYNC, Head amplifier switch, and Chrominance rotate) Timer/counter TM0 (16-bit) TM1 (16-bit) FRC (22-bit) TM3 (16-bit) UDC (5-bit) EC (8-bit) EDV (8-bit) Compare register 3 3 - 2 1 4 1 Number of bits 22 22 16 22 16 22 22 Capture register - 1 6 1 - - - Measurement cycle 125 ns to 524 ms 125 ns to 524 ms 1 s to 65.5 ms 125 ns to 524 ms 1 s to 65.5 ms 125 ns to 524 ms 125 ns to 524 ms Remark
Super timer unit
Timer/counter
Generates HSW signal Divides CFG signal Operation edge
Capture register
Input signal CFG DFG HSW VSYNC CTL TREEL SREEL
Special circuit for VCR
* * * *
VSYNC separator, HSYNC separator VISS detector, Wide-aspect detector Field identifier Head amplifier switch/chrominance rotate output circuit Timer TM2 (16-bit) TM4 (16-bit) TM5 (16-bit) Compare register 1 1 (Capture/compare) 1 Capture register - 1 -
General purpose timer
PWM output
* 16-bit precision: 3 channels (Carrier frequency: 62.5 kHz) * 8-bit precision: 3 channels (Carrier frequency: 62.5 kHz) 3-wire serial I/O: 2 channels * BUSY/STRB control available (only 1 channel) 8-bit resolution x 12 channels, conversion time: 10 s
Serial interface
A/D converter
Note
It is possible to change the capacity of the internal PROM and the internal RAM by specifying the internal memory capacity select (IMS) register.
3
PD78P4916
Function List (2/2)
Item Analog unit * * * * * * Function CTL amplifier RECCTL driver (supports re-write operation) DFG amplifier, DPG comparator, CFG amplifier DPFG separator (Three-value) Reel FG comparator (2 channels) CSYNC comparator
Interrupt External
Programmable 4 levels, vectored interrupt, macro service, context switching 9 (including NMI) 19 (including software interrupt) HALT mode/STOP mode Low-power consumption mode: HALT mode Release from STOP mode by NMI pin's active edge, Watch interrupt (INTW), or INTP1/INTP2/KEY0-KEY4 pins' input.
* *
Internal Standby function
Watch function Power supply voltage Package
0.5-sec interval, capable of low-voltage operation (VDD = 2.7 V) VDD = 2.7 to 5.5 V 100-pin plastic QFP (14 x 20 mm)
4
PD78P4916
Pin Configuration (Top View)
(1) Normal Operation Mode * 100-pin plastic QFP (14 x 20 mm)
PD78P4916GF-3BA
CSYNCIN REEL0IN/INTP3 REEL1IN DFGIN DPGIN CFGCPIN CFGAMPO CFGIN AVDD1 AVSS1 VREFC CTLOUT2 CTLOUT1 CTLIN RECTTL- RECTTL+ CTLDLY AVSS2 ANI11 ANI10
P64 P65/HWIN P66/PWM4 P67/PWM5 P60/STRB/CLO P61/SCK1/BUZ P62/SO1 P63/SI1 PWM0 PWM1 SCK2 SO2 SI2/BUSY VDD XT1 XT2 VSS X2 X1 RESET IC PTO02 PTO01 PTO00 P87/PTO11 P86/PTO10 P85/PWM3 P84/PWM2 P83/ROTC P82/HASW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 2 79 3 78 4 77 76 5 75 6 74 7 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 65 16 64 17 18 63 62 19 61 20 21 60 59 22 58 23 57 24 25 56 55 26 27 54 28 53 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P80 P57 P56 P55 P54 P53 P52 P51 P50 VSS VDD P47 P46 P45 P44 P43 P42 P41 P40 P07
ANI9 ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVDD2 P96 P95/KEY4 P94/KEY3 P93/KEY2 P92/KEY1 P91/KEY0 P90/ENV NMI INTP0 INTP1 INTP2 P00 P01 P02 P03 P04 P05 P06
Caution Connect the IC (Internally Connected) pin to VSS directly.
5
PD78P4916
ANI0-ANI11 AVDD1, AVDD2 AVSS1, AVSS2 AVREF BUSY BUZ CFGAMPO CFGCPIN CFGIN CLO CSYNCIN CTLDLY CTLIN DFGIN DPGIN ENV HASW HWIN IC INTP0-INTP3 KEY0-KEY4 NMI : Analog Input : Analog Power Supply : Analog Ground : Analog Reference Voltage : Serial Busy : Buzzer Output : Capstan FG Amplifier Output : Capstan FG Capacitor Input : Analog Unit Input : Clock Output : Analog Unit Input : Control Delay Input : CTL Amplifier Input Capacitor : Analog Unit Input : Analog Unit Input : Envelope Input : Head Amplifier Switch Output : Hardware Timer External Input : Internally Connected : Interrupt From Peripherals : Key Return : Nonmaskable Interrupt P00-P07 P40-P47 P50-P57 P60-P67 P70-P77 P80, P82-P87 P90-P96 PTO00-PTO02, PTO10, PTO11 PWM0 - PWM5 : Pulse Width Modulation Output RECCTL+, RECCTL- : RECCTL Output/PBCLT Input REEL0IN, REEL1IN : Analog Unit Input RESET ROTC SCK1, SCK2 SI1, SI2 SO1, SO2 STRB VDD VREFC Vss X1, X2 XT1, XT2 : Reset : Chrominance Rotate Output : Serial Clock : Serial Input : Serial Output : Serial Strobe : Power Supply : Reference Amplifier Capacitor : Ground : Crystal (Main System Clock) : Crystal (Subsystem Clock) : Port0 : Port4 : Port5 : Port6 : Port7 : Port8 : Port9 : Programmable Timer Output
CTLOUT1, CTLOUT2 : CTL Amplifier Output
6
PD78P4916
(2) PROM Programming Mode * 100-pin plastic QFP (14 x 20 mm)
PD78P4916GF-3BA
OPEN
(L) OPEN (L) VDD VSS OPEN (L)
OPEN VSS
(L)

OE CE PGM
(L)
OPEN (L)
VDD VSS OPEN VSS OPEN VSS RESET IC/VPP OPEN
(L)
10099 98 97 9695 94 93 92 9190 89 88 87 8685 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 11 70 12 69 68 13 14 67 15 66 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 24 57 56 25 55 26 54 27 53 28 29 52 30 51 31 32 33 34 3536 37 38 39 4041 42 43 44 4546 47 48 49 50

(L)
(L) VDD (L) A9
(L)
Cautions (L) VSS
: Connect to VSS via pull-down resistors individually. : Connect to ground.
OPEN : Leave this pin unconnected. RESET : Apply low level. A0 - A16 : Address Bus D0 - D7 CE OE PGM : Data Bus : Chip Enable : Output Enable : Program RESET VDD VPP VSS : Reset : Power Supply : Programming Power Supply : Ground
(L) A15 A14 A13 A12 A11 A10 A16 A8 VSS VDD A7 A6 A5 A4 A3 A2 A1 A0 D7

D0 D1 D2 D3 D4 D5 D6
7
PD78P4916
Internal Block Diagram
NMI INTP0 INTP3 PWM0 PWM5 PTO00 PTO02 PTO10, PTO11 VREFC REEL0IN REEL1IN CSYNCIN DFGIN DPGIN CFGIN CFGAMPO CFGCPIN CTLOUT1 CTLOUT2 CTLIN RECCTL+ RECCTL - CTLDLY AVDD1, AVDD2 AVSS1, AVSS2 AVREF ANI0 - ANI11 RAM 1536 bytes ROM 62 Kbytes Port0 Port4 Port5 Serial Interface 2 Port6 Port7 Port8 Port9 Super Timer Unit System Control Interrupt Control
VDD VSS X1 X2 XT1 XT2 RESET D0 - D7 A0 - A16 CE OE PGM VPP Used in PROM programming mode
Clock Output Buzzer Output 78K/IV 16-bit CPU Core (RAM 512 bytes)
CLO BUZ
Key Input
KEY0 - KEY4
Analog Unit & A/D Converter
P00 - P07 Real-Time Output Port P80, P82, P83
SI1 SO1 SCK1 SI2/BUSY SO2 SCK2 STRB Serial Interface 1
P00 - P07 P40 - P47 P50 - P57 P60 - P67 P70 - P77 P80, P82 - P87 P90 - P96
8
PD78P4916
System Configuration Example * Camcorder
PD78P4916
DFG DPG Drum motor M Driver DFGIN DPGIN PORT PORT PWM0 PORT SCK1 SI1 SO1 INTP0 Capstan motor M Driver PWM1 INTP0 SCK Microcontroller for camera SO control SI PD78356 PORT Key matrix
CFG
CFGIN
CTL head
RECCTL+ RECCTL- PORT SCK2 SO2 BUSY PORT
Camera block CS CLK DATA BUSY
LCD C/D
Loading motor
M
Driver
PWM2
PD7225
LCD display panel Composite sync signal Audio-video signal processor Video head switch Audio head switch Pseudo-vertical sync signal Signals from remote controller Remote control receive signal CSYNCIN PORT PTO00 PTO01 P80 STRB CS CLK DATA BUSY STB OSD
PD6456
INTP2 X1 X2 XT1
PORT XT2
Mechanical block
PC2800A
16 MHz
32.768 kHz
9
PD78P4916
* Deck-type VCR
PD78P4916
DFG DPG Drum motor DFGIN DPGIN PORT SCK1 SI1 SO1 STB TM CLK FIP C/D DOUT PD16311 DIN
M
Driver
PWM0
CFG
CFGIN PORT SCK2 SO2
FIP
Key matrix
Capstan motor
M
Driver
PWM1
CS OSD CLK PD6454 DATA
CTL head
RECCTL+ RECCTL-
PORT CSYNCIN PTO00 Composite synchronous signal Video head switch Audio head switch Pseudo-vertical synchronous signal Audio-video signal processor unit
Loading motor
M
Driver
PWM2
PTO01 P80
Reel FG0
REEL0IN PWM5
M Reel motors M
Driver
PWM3
Tuner unit PORT
Driver
PWM4
PORT
Mechanical block
Reel FG1
REEL1IN INTP2 Low-frequency oscillation mode X1 X2 XT1 XT2
Remote control receive signal
Signals from remote controller
PC2800A
8 MHz
32.768 kHz
10
PD78P4916
CONTENTS
1. DIFFERENCES BETWEEN PD78P4916 AND PD784915, PD784916A ********************************* 12 2. PIN FUNCTION ********************************************************************************************************************************* 13
2.1 Normal Operation Mode ***************************************************************************************************************************** 13 2.2 PROM Programming Mode (VPP 5 V, RESET = L) ********************************************************************************** 15 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ********************************************************* 16
*
3. INTERNAL MEMORY CAPACITY SELECT REGISTER (IMS) *************************************************** 20 4. PROM PROGRAMMING ******************************************************************************************************************* 21
4.1 4.2 4.3 4.4 Operation Mode ****************************************************************************************************************************************** PROM Write Procedure ****************************************************************************************************************************** PROM Read Procedure ****************************************************************************************************************************** Screening One-time PROM Versions ******************************************************************************************************* 21 23 27 27
5. ELECTRICAL SPECIFICATIONS ***************************************************************************************************** 28 6. PACKAGE DRAWING ********************************************************************************************************************** 46 7. RECOMMENDED SOLDERING CONDITIONS ********************************************************************************* 47 APPENDIX A. DEVELOPMENT TOOLS ********************************************************************************************* 48 APPENDIX B. SOCKET DRAWING AND RECOMMENDED FOOTPRINT **************************************** 50 APPENDIX C. RELATED DOCUMENTS ******************************************************************************************** 52
* * *
11
PD78P4916
*
1. DIFFERENCES BETWEEN PD78P4916 AND PD784915, PD784916A
Other than the memory types, their capacities, and memory-related points, the functions of the three devices are identical: the PD78P4916 incorporates a one-time PROM that is rewritable by users, while the PD784915 and 784916A contain mask ROMs. Table 1-1 shows the differences among these devices. Be sure to keep in mind these differences especially when debugging and pre-producing the application system with the PROM version and then mass-producing it with the mask-ROM version. For the details about the CPU functions and on-chip hardware, refer to the PD784915 Subseries User's Manual--Hardware (U10444E). Table 1-1. Differences among PD784915 Subseries Devices
Parameters Internal ROM
PD78P4916
One-time PROM 62 KbytesNote
PD784915
Mask ROM 48 Kbytes 1280 bytes Not provided
PD784916A
Mask ROM 62 Kbytes 1280 bytes Not provided
Internal RAM Internal memory size select register (IMS) Pinouts Other
2048 bytesNote Provided
Pins related to PROM writing and reading are provided on the PD78P4916. There are differences in noise immunity, noise radiation, and some electrical specifications, because of the differences in circuit complexity and mask layout.
Note
The internal PROM and RAM capacities of the PD78P4916 can be changed through its internal memory size select register (IMS).
Caution There are differences in noise immunity and noise radiation between the PROM and mask-ROM versions. When pre-producing the application set with the PROM version and then massproducing it with the mask-ROM version, be sure to conduct sufficient evaluations for the set using consumer samples (not engineering samples) of the mask-ROM version.
12
PD78P4916
2. PIN FUNCTION 2.1 Normal Operation Mode
(1) Port Pins
Pin Name P00 - P07 Input/Output I/O Alternate function Real-time output port Description 8-bit input/output port (Port0) * Specifiable to input or output mode bitwise. * With software-specifiable on-chip pull-up resistors (P00 - P07). 8-bit input/output port (Port4) * Specifiable to input or output mode bitwise. * With software-specifiable on-chip pull-up resistors (P40 - P47). 8-bit input/output port (Port5) * Specifiable to input or output mode bitwise. * With software-specifiable on-chip pull-up resistors (P50 - P57). 8-bit input/output port (Port6) * Specifiable to input or output mode bitwise. * With software-specifiable on-chip pull-up resistors (P60 - P67).
P40 - P47
I/O
-
P50 - P57
I/O
-
P60 P61 P62 P63 P64 P65 P66 P67 P70 - P77 P80 P82 P83 P84 P85 P86 P87 P90 P91 - P95 P96
I/O
STRB/CLO SCK1/BUZ SO1 SI1 - HWIN PWM4 PWM5
Input I/O
ANI0 - ANI7 Real-time output port
8-bit input port (Port7) for Pseudo-VSYNC output for HASW output for ROTC output 7-bit input/output port (Port8) * Specifiable to input or output mode bitwise. * With software-specifiable on-chip pull-up resistors (P80, P82 - P87)
PWM2 PWM3 PTO10 PTO11 I/O ENV KEY0 - KEY4 - 7-bit input/output port (Port9)
* Specifiable to input or output mode bitwise. * With software-specifiable on-chip pull-up resistors (P90 - P96).
13
PD78P4916
(2) Non-Port Pins (1/2)
Pin Name REEL0IN REEL1IN DFGIN DPGIN CFGIN CSYNCIN CFGCPIN CFGAMPO PTO00 PTO01 PTO02 PTO10 PTO11 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 HASW ROTC ENV SI1 SO1 SCK1 SI2 SO2 SCK2 BUSY STRB ANI0 - ANI7 ANI8 - ANI11 CTLIN CTLOUT1 CTLOUT2 RECCTL+, RECCTL- CTLDLY VREFC NMI - Output I/O I/O - - Input Output Output Input Input Output I/O Input Output I/O Input Output Analog inputs Output Output Output Input/Output Input Alternate function INTP3 - - - - - - - - - - P86 P87 - - P84 P85 P66 P67 P82 P83 P90 P63 P62 P61/BUZ BUSY - - SI2 P60/CLO P70 - P77 - - - - - - - - CTL amplifier input capacitor CTL amplifier output Logic input/CTL amplifier output RECCTL output/PBCTL input External time-constant connection (to rewrite RECCTL) AC ground for VREF amplifier Non-maskable interrupt request input Head amplifier switch output Chrominance rotate output Envelope input Serial data input (Serial interface channel 1) Serial data output (Serial interface channel 1) Serial clock input/output (Serial interface channel 1) Serial data input (Serial interface channel 2) Serial data output (Serial interface channel 2) Serial clock input/output (Serial interface channel 2) Serial busy input (Serial interface channel 2) Serial strobe output (Serial interface channel 2) Analog inputs for A/D converter PWM outputs of super timer unit Drum FG, PFG input (Three-value) Drum PG input Capstan FG input Composite SYNC input CFG comparator input CFG amplifier output Programmable timer outputs of super timer unit Reel FG inputs Description
14
PD78P4916
(2) Non-Port Pins (2/2)
Pin Name INTP0 - INTP2 INTP3 KEY0 - KEY4 CLO BUZ HWIN RESET X1 X2 XT1 XT2 AVDD1, AVDD2 AVSS1, AVSS2 AVREF VDD VSS IC Input/Output Input Input Input Output Output Input Input Input - Input - - - - - - - - - - - - - - Crystal resonator connection for subsystem clock oscillation Crystal resonator connection for clock oscillation of watch Positive power supply for analog unit GND for analog unit Reference voltage input to A/D converter Positive power supply to digital unit GND of digital unit Internally connected. Connect directly to VSS. Alternate function - REEL0IN P91 - P95 P60/STRB P61/SCK1 P65 - - Key input signal Clock output Buzzer output Hardware timer external input Reset input Crystal resonator connection for main system clock oscillation Description External interrupt request input
2.2 PROM Programming Mode (VPP 5 V, RESET = L)
Pin name VPP Input/output - Function Set PROM programming mode High voltage applied at program write/verify operation Low level input for setting PROM programming mode Address input I/O Input Data input/output Program inhibit input in PROM programming mode PROM enable input / programming pulse input Read strobe input to PROM - Positive power supply GND potential
RESET A0 - A16 D0 - D7 PGM CE OE VDD VSS
Input
15
PD78P4916
*
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the input/output circuit types of the device's pins and the recommended connection of the pins which are unnecessary to the user's application. The circuit diagrams for the I/O circuits are shown in Figure 2-1. Table 2-1.
Pins P00-P07 P40-P47 P50-P57 P60/STRB/CLO P61/SCK1/BUZ P62/SO1 P63/SI1 P64 P65/HWIN P66/PWM4 P67/PWM5 P70/ANI0-P77/ANI7 P80 P82/HASW P83/ROTC P84/PWM2 P85/PWM3 P86/PTO10 P87/PTO11 P90/ENV P91/KEY0-P95/KEY4 P96 SI2/BUSY SO2 SCK2 ANI8-ANI11 RECCTL+, RECCTL-
Pin I/O Circuits and Recommended Connection of Unused Pins (1/2)
I/O circuit types 5-A Direction I/O Recommended connection of unused pins Input mode: Connect to VDD. Output mode: Leave unconnected.
8-A 5-A 8-A 5-A 8-A 5-A 9 5-A Input I/O Connect to VSS. Input mode: Connect to VDD. Output mode: Leave unconnected.
8-A 5-A 2-A 4 8-A 7 --
Input Output I/O Input I/O
Connect to VDD. High-impedance mode: Connect to VSS via a pull-down resistor. Otherwise: Leave unconnected. Input mode: Connect to VDD. Output mode: Leave unconnected. Connect to VSS. When ENCTL = 0 and ENREC = 0: Connect to VSS.
Remark ENCTL: Bit 1 of the amplifier control register (AMPC) ENREC: Bit 7 of the amplifier mode register 0 (AMPM0)
16
PD78P4916
Table 2-1.
Pins DFGIN DPGIN CFGIN, CFGCPIN CSYNCIN REEL0IN/INTP3, REEL1IN CTLOUT1 CTLOUT2 CFGAMPO CTLIN VREFC CTLDLY PWM0, PWM1 PTO00-PTO02 NMI INTP0 INTP1, INTP2 AVDD1, AVDD2 AVREF, AVSS1, AVSS2 RESET XT1 XT2 IC
Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)
I/O circuit types -- Direction Input Recommended connection of unused pins ENDRUM = 0: Connect to VSS. ENDRUM = 0, or ENDRUM = 1 and SELPGSEPA = 0: Connect to VSS. ENCAP = 0: Connect to VSS. ENCSYN = 0: Connect to VSS. ENREEL = 0: Connect to VSS. Leave unconnected. When ENCTL and ENCOMP = 0 and 0: Connect to VSS. ENCTL = 1: Leave unconnected. Leave unconnected. When ENCTL = 0: Leave unconnected. When ENCTL, ENCAP, and ENCOMP = 0, 0, and 0: Leave unconnected. Leave unconnected. Leave unconnected. Connect to VDD. Connect to VDD or VSS. Connect to VDD. Connect to VDD. Connect to VSS. -- Connect to VSS. Leave unconnected. Connect directly to VSS.
-- -- -- --
Output I/O Output --
3 2 2-A -- 2 --
Output Input Input -- -- --
Remark
ENDRUM: ENCAP: ENCSYN: ENREEL: ENCTL: ENCOMP:
Bit 2 of the amplifier control register (AMPC) Bit 3 of the amplifier control register (AMPC) Bit 5 of the amplifier control register (AMPC) Bit 6 of the amplifier control register (AMPC) Bit 1 of the amplifier control register (AMPC) Bit 4 of the amplifier control register (AMPC)
SELPGSEPA: Bit 2 of the amplifier mode register 0 (AMPM0)
17
PD78P4916
Figure 2-1. Pin I/O Circuit Diagrams (1/2)
Type 2
Type 5-A VDD IN pullup enable VDD data P-ch
Schmitt triggered input with hysteresis characteristics.
Type 2-A VDD output disable
P-ch IN/ OUT N-ch
P-ch
pullup enable
IN
input enable
Schmitt triggered input with hysteresis characteristics. Type 7 Type 3 VDD P-ch data N-ch OUT VREF (Threshold voltage) IN P-ch N-ch Comparator
Type 8-A Type 4 VDD data P-ch OUT output disable N-ch output disable Push-pull output that can also set the output to the high-impedance state (both P-ch and N-ch transistors are turned off.) N-ch data pullup enable VDD P-ch IN/ OUT VDD
P-ch
18
PD78P4916
Figure 2-1. Pin I/O Circuit Diagrams (2/2)
Type 9
IN
P-ch N-ch
Comparator
VREF (Threshold voltage)
input enable
19
PD78P4916
3. INTERNAL MEMORY CAPACITY SELECT REGISTER (IMS)
Internal memory capacity select register (IMS) specifies the effective area of on-chip memory (PROM, RAM) of the PD78P4916. Setting this register is required when the capacity of the ROM or RAM in the mask version is smaller than that of the PD78P4916. If the memory capacity of the PD78P4916 is appropriately defined using this register, bugs in application programs due to accessing an address beyond the memory capacity of the actual chip can be avoided. The IMS register is write-only register. To write this register, use the 8-bit manipulation instruction. The register is initialized to FFH by RESET input (ROM: 62 Kbytes, RAM: 2048 bytes).
*
7 IMS 1
Figure 3-1. Internal Memory Capacity Select Register (IMS) Format
6 1
5
4
3 1
2 1
1
0
Address FFFCH
State at reset R/W FFH W
ROM1 ROM0
RAM1 RAM0
RAM1 RAM0 0 1 Other ROM1 ROM0 1 1 0 1 Other 1 1
Specification of internal RAM capacity 1280 bytes 2048 bytes Setting prohibited
Specification of internal ROM capacity 48 Kbytes 62 Kbytes Setting prohibited
Caution The PD78P4916 has the IMS and the PD784915 and 784916A do not have it. However, if a write instruction to IMS is executed in the PD784915 or 784916A, it does not cause conflicts or malfunctions.
20
PD78P4916
4. PROM PROGRAMMING
The PD78P4916 has on-chip 62-Kbyte PROM as the program memory. The PROM programming mode is entered by setting VDD, IC/VPP, and RESET pins as specified. For the settings of the unused pins in this mode, refer to the drawing of "(2) PROM Programming Mode" in the section "Pin Configuration (Top View)".
4.1 Operation Mode
The PROM programming mode is entered by applying +5 V or +12 V to the IC/VPP pin, +5 V or +6.5 V to the VDD pins, and low-level voltage to the RESET pin. Table 4-1 shows the operation mode specified by the CE, OE, and PGM pins. It is possible to read the contents of PROM by setting up read operation mode. Table 4-1. Operation Mode of PROM Programming
Pins Operation mode Page data latch Page write Byte write Program verify Program inhibit
RESET L
IC/VPP +12.5 V
VDD +6.5 V
CE H H L L x x
OE L H H L H L L H x
PGM H L L H H L H x x
D0 - D7 Data input High impedance Data input Data output High impedance
Read Output disable Standby
+5 V
+5 V
L L H
Data output High impedance High impedance
Remark x : Low or high level
21
PD78P4916
(1) Read mode By setting CE = L and OE = L, the device enters the read mode. (2) Output disable mode By setting OE = H, the device enters the output disable mode, where data output pins go to high impedance state. Therefore it is possible to read data from a specified device by enabling only the OE pin of the device to be read, if two or more PD78P4916s are connected to a data bus. (3) Standby mode By setting CE = H, the device enters the Standby mode. In this mode, data output pins go to high impedance state regardless of the OE pin condition. (4) Page data latch mode By setting CE = H, PGM = H, and OE = L at the beginning of page programming mode, the device enters the page data latch mode. In this mode, 4-byte data are latched in page units (consisting of 4 bytes) to internal address/data latch circuit. (5) Page programming mode After one-page data (consisting of 4 bytes) and their address are latched in the page data latch mode, the page programming operation is executed by applying 0.1-ms programming pulse (active low) to the PGM pin under CE = H, OE = H conditions. Following that operation, the programming data is verified by setting CE = L and OE = L. When data is not programmed by one programming pulse, the write and verify operations are repeated X times (X 10). (6) Byte programming mode Applying 0.1-ms programming pulse (active low) to the PGM pin under CE = L and OE = H condition, byte programming operation is executed. Next, the programming data is verified by setting OE = L. When data is not programmed by one programming pulse, the write and verify operations are repeated X times (X 10). (7) Program verify mode By setting CE = L, PGM = H, and OE = L, the device enters the program verify mode. Check whether data is programmed correctly or not in this mode after write operation. (8) Program inhibit mode When the OE pins, VPP pins, and D0-D7 pins of two or more PD78P4916s are connected in parallel, use program inhibit mode to write data to one of those devices. Programming is executed in the page programming mode or byte programming mode as mentioned above. At that time, data is not programmed to a device for which high level voltage is applied to the PGM pin.
22
PD78P4916
4.2 PROM Write Procedure
Figure 4-1. Flowchart in Page Programming Mode
Start Address = G VDD = 6.5 V, VPP = 12.5 V
X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch
X = X+1 0.1-ms programming pulse Fail
No X = 10? Yes
Verify 4 bytes Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD
Pass
Verify all bytes All Pass Write operation end
Fail
Defective
Remarks 1. G = Start address 2. N = End address of the program
23
PD78P4916
Figure 4-2. Operation Timing in Page Programming Mode
Page data latch
Page programming
Program verify
A2 - A16
Address input
A0, A1
Address input
D0 - D7
Hi-Z Data input
Hi-Z Data output
Hi-Z
VPP VPP VDD VDD+1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL
24
PD78P4916
Figure 4-3. Flowchart in Byte Programming Mode
Start Address = G VDD = 6.5 V, VPP = 12.5 V
X=0
X = X+1 Address = Address + 1 0.1-ms programming pulse Fail
No X = 10? Yes
Verify Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD
Pass
Verify all bytes All Pass Write operation end
Fail
Defective
Remarks 1. G = Start address 2. N = End address of the program
25
PD78P4916
Figure 4-4. Operation Timing in Byte Programming Mode
Programming Program verify
A0 - A16
Address input
D0 - D7
Hi-Z
Data input
Hi-Z
Data output
Hi-Z
VPP VPP VDD VDD+1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL
Cautions 1. Apply voltage to VDD before applying voltage to VPP, and cut off VDD voltage after VPP voltage is cut off. 2. The voltage including overshoot applied to VPP pin must be kept less than +13.5 V. 3. If a device is inserted or removed while +12.5 V is applied to VPP pin, it may be adversely affected in reliability.
26
PD78P4916
4.3 PROM Read Procedure
The contents of PROM can be read onto external data bus (D0-D7) as described below: (1) Fix RESET pin to low and supply +5 V to VPP pin. Connect other unused pins as specified in "(2) PROM Programming Mode" in section "Pin Configuration (Top View)." (2) Supply +5 V to the VDD and VPP pins. (3) Input the address of the data to be read to the A0-A16 pins. (4) Enter the read mode (CE = L, OE = L). (5) Output data to D0-D7 pins. The above operation timing from (2) to (5) is shown in Figure 4-5. Figure 4-5. PROM Read Timing
A0 - A16
Address input
CE (Input)
OE (Input)
D0 - D7
Hi-Z
Data output
Hi-Z
4.4 Screening One-time PROM Versions
The one-time PROM version (PD78P4916GF-3BA) cannot be completely tested by NEC for shipment because of its structure. For screening, it is recommended to verify PROM after storing the necessary data under the following conditions:
Storage Temperature 125 C Storage Time 24 hours
27
PD78P4916
*
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 C)
Parameter Supply voltage Symbol VDD AVDD1 AVDD2 AVSS1 AVSS2 Input voltage Analog input voltage (ANI0-ANI11) Output voltage Output current, low VO IOL Per pin Total of all output pins Output current, high IOH Per pin Total of all output pins Operating ambient temperature Storage temperature TA VI VIAN VDD AVDD2 VDD < AVDD2 Conditions VDD - AVDD1 0.5 V VDD - AVDD2 0.5 V AVDD1 - AVDD2 0.5 V Ratings -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +0.5 -0.5 to +0.5 -0.5 to VDD+0.5 -0.5 to AVDD2+0.5 -0.5 to VDD+0.5 -0.5 to VDD+0.5 15 100 -10 -50 -10 to +70 Unit V V V V V V V V V mA mA mA mA C
Tstg
-65 to +150
C
Caution If any of the above parameters exceeds the absolute maximum ratings, even momentarily, device reliability may be impaired. The absolute maximum ratings are values that may physically damage the product. Be sure to use the product within the ratings. Operating Conditions
Operating ambient temperature (TA) -10 to +70 C
Clock frequency 4 MHz fXX 16 MHz
Operating condition All functions CPU function only
Supply voltage (VDD) +4.5 to +5.5 V +4.0 to +5.5 V +2.7 to +5.5 V
32 kHz fXT 35 kHz
Subclock operation (CPU, watch, and Port functions only)
28
PD78P4916
Oscillator Characteristics (Main Clock) (TA = -10 to +70 C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Resonator Crystal resonator Recommended circuit Item Oscillation frequency (fXX) MIN. 4 MAX. 16 Unit MHz
X1
X2 VSS
C1
C2
Oscillator Characteristics (Subclock) (TA = -10 to +70 C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)
Resonator Crystal resonator Recommended circuit Item Oscillation frequency (fXT) MIN. 32 MAX. 35 Unit kHz
XT1
XT2 VSS
C1
C2
Caution When using the main system clock and subsystem clock oscillators, wiring in the area enclosed with the dotted lines should be carried out as follows to avoid an adverse effect from wiring capacitance: * Wiring should be as short as possible. * Wiring should not cross other signal lines. Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS. Do not ground wiring to a ground pattern in which high current flows. * Do not fetch a signal from the oscillator. As the amplification degree of the subsystem clock oscillator is low to reduce current consumption, pay particular attention to the wiring method.
29
PD78P4916
DC Characteristics (TA = -10 to +70 C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Input voltage, low Symbol VIL1 VIL2 VIL3 Input voltage, high VIH1 VIH2 VIH3 Output voltage, low VOL1 VOL2 VOL3 Output voltage, high Input leakage current Output leakage current VDD power supply current VOH1 VOH2 ILI ILO Conditions Other than pins indicated in Note 1 below Pins indicated in Note 1 below X1, X2 Other than pins indicated in Note 1 below Pins indicated in Note 1 below X1, X2 IOL = 5.0 mA (Pins listed in Note 2 below) IOL = 2.0 mA IOL = 100 A IOH = -1.0 mA IOH = -100 A 0 VI VDD 0 VO VDD VDD-1.0 VDD-0.4 10 10 MIN. 0 0 0 0.7VDD 0.8VDD VDD-0.5 TYP. MAX. 0.3VDD 0.2VDD 0.4 VDD VDD VDD 0.6 0.45 0.25 Unit V V V V V V V V V V V
A A
mA
IDD1
Operation mode
fXX = 16 MHz fXX = 8 MHz (Low frequency oscillation mode) Internal main clock operation at 8 MHz fXT = 32.768 kHz Subclock operation (CPU, Watch, Port) VDD = 2.7 V
35
55
0.9
1.2
mA
IDD2
HALT mode
fXX = 16 MHz fXX = 8 MHz (Low frequency oscillation mode) Internal main clock operation at 8 MHz fXT = 32.768 kHz Subclock operation (CPU, Watch, Port) VDD = 2.7 V
15
27.5
mA
30
60
A
Data retention voltage Data retention current Note 3
VDDDR IDDDR
STOP mode STOP mode VDDDR = 5.0 V STOP mode VDDDR = 2.7 V STOP mode VDDDR = 2.5 V Subclock oscillation
2.5 36 75
V
A A A
k
Subclock oscillation
3.5
15
Subclock suspended
1.5
10
Pull-up resistor
RL
VI = 0 V
25
55
110
Notes 1. RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/KEY4. 2. P46, P47 3. When subclock is suspended at STOP mode, disconnect feedback resistor and connect XT1 pin to the VDD potential.
30
PD78P4916
AC Characteristics CPU and peripheral unit operation clocks (TA = -10 to +70 C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter CPU operation clock cycle time Symbol tCLK Conditions fXX = 16 MHz VDD = AVDD = 4.0 to 5.5 V CPU function only fXX = 16 MHz fXX = 8 MHz, Low frequency oscillation mode (CC bit7 = 1) Peripheral unit operation clock cycle time tCLK1 fXX = 16 MHz fXX = 8 MHz, Low frequency oscillation mode (CC bit7 = 1) 125 ns TYP. 125 Unit ns
Serial interface (1) SIOn: n = 1, 2 (TA = -10 to +70 C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Serial clock cycle time Symbol tCYSK Input Output Conditions External clock fCLK1/8 fCLK1/16 fCLK1/32 fCLK1/64 fCLK1/128 fCLK1/256 Serial clock high/low level width tWSKH tWSKL SIn set-up time (to SCKn ) SIn hold time (from SCKn ) SOn output delay time (from SCKn ) tSSSK tHSSK tDSSK Input Output External clock Internal clock MIN. 1.0 1.0 2.0 4.0 8.0 16 32 420 tCYSK/2-50 100 400 0 300 MAX. Unit
s s s s s s s
ns ns ns ns ns
Remarks 1. fCLK1: Operation clock for peripheral unit (8 MHz) 2. n = 1, 2
(2) Only SIO2 (TA= -10 to +70 C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter SCK2(8) STRB Strobe high level width BUSY setup time (to BUSY detection timing) BUSY hold time (from BUSY detection timing) Busy inactive SCK2(1) Symbol tDSTRB tWSTRB tSBUSY tHBUSY tLBUSY Conditions MIN. tWSKH MAX. tCYSK ns ns ns tCYSK+tWSKH Unit
tCYSK-30 tCYSK+30 100 100
Remarks 1. The value in the parentheses following SCK2 indicates the sequential number of the SCK2. 2. BUSY detection timing is (n + 2) x tCYSK (n = 0, 1,...) after SCK2(8) . 3. BUSY inactive SCK2(1) is a value at the time data is already written in SIO2.
31
PD78P4916
Other Operations (TA = -10 to +70 C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Timer unit input low level width Symbol tWCTL Conditions at DFGIN, CFGIN, DPGIN, REEL0IN, REEL1IN logic level input at DFGIN, CFGIN, DPGIN, REEL0IN, REEL1IN logic level input DFGIN, CFGIN and DPGIN input MIN. tCLK1 MAX. Unit ns
Timer unit input high level width
tWCTH
tCLK1
ns
Timer unit input signal valid edge input cycle CSYNCIN low level width
tPERIN
2
s
ns ns
tWCR1L
Digital noise eliminator not used Digital noise eliminator used (INTM2 bit 4 = 0) Digital noise eliminator used (INTM2 bit 4 = 1)
8tCLK1 108tCLK1
180tCLK1
ns
CSYNCIN high level width
tWCR1H
Digital noise eliminator not used Digital noise eliminator used (INTM2 bit 4 = 0) Digital noise eliminator used (INTM2 bit 4 = 1)
8tCLK1 108tCLK1
ns ns
180tCLK1
ns
Digital noise eliminator
Eliminated pulse width Passed pulse width
tWSEP
INTM2 bit 4 = 0 INTM2 bit 4 = 1 INTM2 bit 4 = 0 INTM2 bit 4 = 1 108tCLK1 180tCLK1 10 10 2tCLK1 2tCLK1 Other than in STOP mode When cancelling STOP mode 2tCLK1 10 2tCLK1 10 2tCLK1 32
Note
104tCLK1 176tCLK1
ns ns ns ns
NMI low level width NMI high level width INTP0 and INTP3 low level width INTP0 and INTP3 high level width INTP1, KEY0 - KEY4 low level width INTP1, KEY0 - KEY4 high level width INTP2 low level width
tWNIL tWNIH tWIPL0 tWIPH0 tWIPL1
VDD = AVDD = 2.7 to 5.5 V VDD = AVDD = 2.7 to 5.5 V
s s
ns ns ns
s
ns
tWIPH1
Other than in STOP mode When cancelling STOP mode
s
ns
tWIPL2
Main clock operation in normal mode Subclock operation in normal mode
Sampled at fCLK Sampled at fCLK/128 Sampled at fCLK Sampled at fCLK/128
s s
ms
61 7.9
Note
When cancelling STOP mode INTP2 high level width tWIPH2 Main clock operation in normal mode Subclock operation in normal mode Sampled at fCLK Sampled at fCLK/128 Sampled at fCLK Sampled at fCLK/128
10 2tCLK1 32
Note
s
ns
s s
ms
61 7.9
Note
When cancelling STOP mode RESET low level width tWRSL
10 10
s s
Note
If a high level or low level is input two times in succession during the sampling period, high level or low level is detected.
Remark tCLK1: Operation clock cycle time for peripheral unit (125 ns).
32
PD78P4916
Clock Output Operation (TA = -10 to +70 C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter CLO cycle time CLO low level width CLO high level width CLO rising time CLO falling time Symbol tCYCL tCLL tCLH tCLR tCLF tCYCL/2 50 tCYCL/2 50 Expression MIN. 250 75 75 MAX. 2000 1050 1050 50 50 Unit ns ns ns ns ns
Data Retention Characteristics (TA = -10 to +70 C, VDD = AVDD = 2.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Input voltage, low Input voltage, high Symbol VIL VIH Conditions Pins listed in Note below MIN. 0 0.9VDDDR TYP. MAX. 0.1VDDDR VDDDR Unit V V
Note
RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/KEY4
Watch Function (TA = -10 to +70 C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter Subclock oscillation retention voltage Hardware watch function operation voltage Symbol VDDXT Conditions MIN. 2.7 MAX. Unit V
VDDW
2.7
V
Subclock Oscillation Suspension Detection Flag (TA = -10 to +70 C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Oscillation suspension detection width Symbol tOSCF Conditions MIN. 45 MAX. Unit
s
A/D Converter Characteristics (TA = -10 to +70 C, VDD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Total error Quantization error Conversion time tCONV ADM bit 4 = 0 ADM bit 4 = 1 Sampling time tSAMP ADM bit 4 = 0 ADM bit 4 = 1 Analog input voltage Analog input impedance AVREF current VIAN ZAN AIREF 160tCLK1 80tCLK1 32tCLK1 16tCLK1 0 1000 0.4 1.2 AVREF AVREF = VDD Symbol Conditions MIN. 8 2.0 1/2 TYP. MAX. Unit bit % LSB
s s s s
V M mA
33
PD78P4916
VREF Amplifier (TA = 25 C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Reference voltage Charge current Symbol VREF ICHG AMPM0.0 is set to 1 for pins listed in Note below. Conditions MIN. 2.35 300 TYP. 2.50 MAX. 2.65 Unit V
A
Note
RECCTL+, RECCTL-, CFGIN, CFGCPIN, DFGIN, DPGIN, CSYNCIN, REEL0IN, REEL1IN
CTL Amplifier (TA = 25 C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter CTL+, - input resistance Feedback resistance Bias resistance Minimum voltage gain Maximum voltage gain Gain switching step Common mode signal rejection Comparator set voltage for waveform regulation, high Comparator reset voltage for waveform regulation, high Comparator set voltage for waveform regulation, low Comparator reset voltage for waveform regulation, low Comparator high voltage for CLT flag S Comparator low voltage for CLT flag S Comparator high voltage for CLT flag L Comparator low voltage for CLT flag L VPBCTLLS VREF-0.53 VREF-0.50 VREF-0.47 V Symbol RICTL RFCTL RBCTL GCTLMIN GCTLMAX SGAIN CMR VPBCTLHS DC, Voltage gain: 20 dB Conditions MIN. 2 20 20 17 71 TYP. 5 50 50 20 75 1.77 50 VREF+0.47 VREF+0.50 VREF+0.53 MAX. 10 100 100 22 Unit k k k dB dB dB dB V
VPBCTLHR
VREF+0.27 VREF+0.30 VREF+0.33
V
VPBCTLLR
VREF-0.33 VREF-0.30 VREF-0.27
V
VFSH VFSL VFLH VFLL
VREF+1.00 VREF+1.05 VREF+1.10 VREF-1.10 VREF-1.05 VREF-1.00 VREF+1.40 VREF+1.45 VREF+1.50 VREF-1.50 VREF-1.45 VREF-1.40
V V V V
34
PD78P4916
CFG Amplifier (AC Coupling) (TA = 25 C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Voltage gain 1 Voltage gain 2 CFGAMPO output current, high CFGAMPO output current, low Comparator high voltage Comparator low voltage Duty precision Symbol GCFG1 GCFG2 IOHCFG IOLCFG VCFGH VCFGL PDUTY See Note below. Conditions fi = 2 kHz, open loop fi = 2 kHz, open loop DC DC MIN. 50 34 -1 0.4 VREF+0.09 VREF+0.12 VREF+0.15 VREF-0.15 VREF-0.12 VREF-0.09 49.7 50.0 50.3 TYP. MAX. Unit dB dB mA mA V V %
Note
The following circuit and input signal conditions are assumed. * Input signal: sine wave input (5 mVp-p), fi = 1 kHz * Voltage gain: 50 dB
22 F 330 k CFGAMPO 0.01 F CFGCPIN CFGIN
PD78P4916
1 k
DFG Amplifier (AC Coupling) (TA = 25 C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Voltage gain Feedback resistance Input protect resistance Comparator high voltage Comparator low voltage Symbol GDFG RFDFG RIDFG VDFGH VDFGL Conditions fi = 900 Hz, open loop MIN. 50 160 400 150 VREF+0.07 VREF+0.10 VREF+0.14 VREF-0.14 VREF-0.10 VREF-0.07 640 TYP. MAX. Unit dB k V V
Caution The resistance of the pin to be connected to the DFGIN pin must be below 16 k. If the resistance is higher than the limit, the DFG amplifier may oscillate.
DPG Comparator (AC Coupling) (TA = 25 C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance Comparator high voltage Comparator low voltage Symbol ZIDPG VDPGH VDPGL Conditions MIN. 20 TYP. 50 MAX. 100 Unit k V V
VREF+0.02 VREF+0.05 VREF+0.08 VREF-0.08 VREF-0.05 VREF-0.02
35
PD78P4916
Three-value divider (TA = 25 C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance Comparator high voltage Comparator low voltage Symbol ZIPFG VPFGH VPFGL Conditions MIN. 20 TYP. 50 MAX. 100 Unit k V V
VREF+0.5 VREF+0.7 VREF+0.9 VREF-1.4 VREF-1.2 VREF-1.0
CSYNC Comparator (AC Coupling) (TA = 25 C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance Comparator high voltage Comparator low voltage Symbol ZICSYN VCSYNH VCSYNL Conditions MIN. 20 TYP. 50 MAX. 100 Unit k V V
VREF+0.07 VREF+0.10 VREF+0.13 VREF-0.13 VREF-0.10 VREF-0.07
Reel FG Comparator (AC Coupling) (TA = 25 C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance Comparator high voltage Comparator low voltage Symbol ZIRLFG VRLFGH VRLFGL Conditions MIN. 20 TYP. 50 MAX. 100 Unit k V V
VREF+0.02 VREF+0.05 VREF+0.08 VREF-0.08 VREF-0.05 VREF-0.02
RECCTL Driver (TA = 25 C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter RECCTL+, - high level output voltage RECCTL+, - low level output voltage CTLDLY on-chip resistor CTLDLY charge current CTLDLY discharge current Symbol VOHREC VOLREC RCTL IOHCTL IOLCTL On-chip resistor disabled Conditions IOH = -4 mA IOL = 4 mA 40 -3 -3 70 MIN. VDD-0.8 0.8 140 TYP. MAX. Unit V V k mA mA
36
PD78P4916
Timing Waveform AC timing test point
0.8 VDD or 2.2 V Test points 0.8 V 0.8 V 0.8 VDD or 2.2 V
Serial Transfer Timing (SIOn: n = 1, 2)
tWSKL SCKn tCYSK SIn tSSSK tHSSK tWSKH
Input data
tDSSK SOn Output data
37
PD78P4916
Serial Transfer Timing (Only SIO2) No busy processing
tWSKL SCK2 7 tCYSK BUSY At active-high tDSTRB STRB Invalid busy tWSTRB tWSKH 8 9 10 1 2
Continue busy processing
tWSKL SCK2 7 tCYSK BUSY At active-high tDSTRB STRB tWSTRB tWSKH 8 9 tSBUSY 10 10+n tHBUSY
Terminate busy processing
tWSKL SCK2 7 tCYSK BUSY At active-high tWSKH 8 9 10+n tHBUSY 11+n tLBUSY 1
Caution Do not use busy control and strobe control whenever the external clock is selected as a serial clock.
38
PD78P4916
Super timer unit input timing
tWCTH At DFGIN, CFGIN, DPGIN, REEL0IN and REEL1IN logic level input 0.8 VDD 0.8 V tWCTL
tWCR1H 0.8 VDD At CSYNCIN logic level input 0.8 V
tWCR1L
Interrupt input timing
tWNIH 0.8 VDD NMI 0.8 V
tWNIL
tWIPH0 0.8 VDD INTP0, INTP3 0.8 V
tWIPL0
tWIPH1 0.8 VDD INTP1, KEY0 - KEY4 0.8 V
tWIPL1
tWIPH2 0.8 VDD INTP2 0.8 V
tWIPL2
Reset input timing
tWRSL
RESET 0.8 V
39
PD78P4916
Clock output timing
tCLH CLO 0.8 VDD 0.8 V tCLR tCLF tCLL tCYCL
40
PD78P4916
DC Programming Characteristics (TA = +25 5 C, VSS = AVSS = 0 V)
Parameter Input voltage, high Input voltage, low Input leakage current Output voltage, high Symbol VIH VIL ILIP VOH1 VOH2 Output voltage, low Output leakage current VDD supply voltage VOL ILO VDDP VDD Symbol VIH VIL ILI VOH1 VOH2 VOL 0 VI VDDP
Note 2
Note 1
Conditions
MIN. 2.4 -0.3
TYP.
MAX. VDDP+0.3 0.8 10
Unit V V
A
V V
IOH = -400 A IOH = -100 A IOL = 2.1 mA 0 VO VDDP, OE = VIH Program memory write mode Program memory read mode
2.4 VDDP-0.7 0.45 10 6.25 6.5 6.75
V
A
V
4.50
5.0
5.50
V
VPP supply voltage
VPP
VPP
Program memory write mode Program memory read mode
12.2
12.5
12.8
V
VPP = VDDP
V
VDD supply current
IDD
IDD
Program memory write mode Program memory read mode
50
mA
30
mA
VPP supply current
IPP
IPP
Program memory write mode Program memory read mode 1
50
mA
100
A
Notes 1. Corresponding symbols of the PD27C1001A. 2. VDDP is a VDD pin during programming.
41
PD78P4916
AC Programming Characteristics (TA = +25 5 C, VSS = AVSS = 0 V) PROM Write Operation Mode (Page Programming Mode)
Parameter Address setup time CE set time Input data setup time Address hold time Symbol Note 1 tAS tCES tDS tAH tAHL tAHV Input data hold time Output data hold time VPP setup time VDDP setup time Initial programming pulse width OE set time OE valid data delay time OE pulse width during data latch PGM set-up time CE hold time OE hold time tDH tDF tVPS tVDS
Note 2
Conditions
MIN. 2 2 2 2 2 0 2 0 2 2 0.095 2
TYP.
MAX.
Unit
s s s s s s s
230 ns
s s
0.1 0.105 ms
tPW tOES tOE tLW tPGMS tCEH tOEH
s
1
s s s s s
1 2 2 2
Notes 1. Correspond to symbols of the PD27C1001A (except tVDS). 2. tVDS corresponds to tVCS of the PD27C1001A.
42
PD78P4916
PROM Write Mode (Byte Programming Mode)
Parameter Address setup time CE set time Input data setup time Address hold time Input data hold time Output data hold time VPP setup time VDDP setup time Initial programming pulse width OE set time OE valid data delay time Symbol Note 1 tAS tCES tDS tAH tDH tDF tVPS tVDS
Note 2
Conditions
MIN. 2 2 2 2 2 0 2 2 0.095 2
TYP.
MAX.
Unit
s s s s s
130 ns
s s
0.1 0.105 ms
tPW tOES tOE
s
150 ns
Notes 1. Correspond to symbols of the PD27C1001A (except tVDS). 2. tVDS corresponds to tVCS of the PD27C1001A. PROM Read Mode
Parameter Address data output time CE data output time OE data output time Data hold time (from OE , CE ) Note 2 Data hold time (from address) Symbol Note 1 tACC tCE tOE tDF tOH Conditions CE = OE = VIL OE = VIL CE = VIL CE = VIL or OE = VIL CE = OE = VIL 0 0 MIN. TYP. MAX. 200 200 75 60 Unit ns ns ns ns ns
Notes 1. Correspond to symbols of the PD27C1001A. 2. tDF is a time after either OE or CE rose to VIH first.
43
PD78P4916
PROM Write Mode Timing (Page Programming Mode)
Page data latch A2 - A16 tAS A0, A1 tDS D0 - D7 Hi-Z tVPS VPP VPP VDDP tVDS VDDP +1.5 VDDP VDDP Data input tDH tAHL
Page programming
Program verify
tAHV
tDH Hi-Z tPGMS tOE Data output tAH Hi-Z
tCES VIH CE VIL VIH PGM VIL VIH OE VIL tLW tOES tPW tCEH
tOEH
44
PD78P4916
PROM Write Mode Timing (Byte Programming Mode)
Programming
Program verify
A0 - A16 tAS D0 - D7 Hi-Z tDS VPP VPP VDDP tVPS VDD+1.5 VDDP VDDP tVDS VIH CE VIL tCES VIH PGM VIL VIH OE VIL tOES tOE tPW Data input tDH Hi-Z Data output tAH tDF Hi-Z
Cautions 1. Apply voltage to VDDP before applying voltage to VPP, and cut off VDDP voltage after VPP voltage is cut off. 2. The voltage, including overshoot, applied to VPP pin must be kept less than +13.5 V. 3. If a device is inserted or removed while +12.5 V is applied to VPP pin, it may be adversely affected in reliability.
PROM Read Mode Timing
A0 - A16
Valid address
CE tCE OE tOENote 1 tACCNote 1 D0 - D7 Hi-Z tOH Data output Hi-Z tDFNote 2
Notes 1. If data need to be read within tACC, the maximum delay time of OE active level input from CE falling should be tACC - tOE. 2. tDF is the time after either OE or CE first rose to VIH.
45
PD78P4916
6. PACKAGE DRAWING
100 PIN PLASTIC QFP (14 x 20)
A B
80 81
51 50
detail of lead end
C
D
S
100 1
31 30
F
G
H
IM
J K
P
N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S
L P100GF-65-3BA1-2 MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 0.8 0.6 0.30 0.10 0.15 0.65 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.031 0.024 0.012+0.004 -0.005 0.006 0.026 (T.P.) 0.071+0.008 -0.009 0.031+0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
46
M
55
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PD78P4916
7. RECOMMENDED SOLDERING CONDITIONS
This device should be soldered and mounted under the following conditions. For details about the recommended conditions, refer to the document "Semiconductor Device Mounting Technology Manual" (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 7-1. Surface Mounting Type Soldering Conditions
*
PD78P4916GF-3BA: 100-pin plastic QFP (14 x 20 mm)
Soldering Method Infrared rays reflow Soldering Conditions Peak package's surface temperature: 235 C, Reflow time: 30 seconds or less (at 210 C or higher), Number of reflow processes: 2 or less (1) Wait for the device temperature to come down to room temperature after the first reflow before starting the second reflow. (2) Do not perform flux cleaning of the soldered portion after the first reflow. Peak package's surface temperature: 215 C, Reflow time: 40 seconds or less (at 200 C or higher), Number of reflow processes: 2 or less (1) Wait for the device temperature to come down to room temperature after the first reflow before starting the second reflow. (2) Do not perform flux cleaning of the soldered portion after the first reflow. Symbol IR35-00-2
VPS
VP15-00-2
Wave soldering
Solder temperature: 260 C or below, Flow time: 10 seconds or less, Number of flow WS60-00-1 process: 1, Preheating temperature; 120 C max. (package surface temperature) Pin temperature: 300 C or below, Time: 3 seconds or less (per pin row) --
Partial heating
Caution Do not use different soldering methods together (except for partial heating).
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PD78P4916
*
APPENDIX A.
DEVELOPMENT TOOLS
The following development tools are prepared for system development using the PD78P4916. Language Software
RA78K4 CC78K4
Note 1 Note 1 Note 1
Assembler package common to the 78K/IV Series C compiler package common to the 78K/IV Series C compiler library source file common to the 78K/IV Series
CC78K4-L
PROM Writing Tool
PG-1500 PA-78P4916GF PG-1500 Controller
Note 2
PROM programmer Programmer adapter connected to the PG-1500 Control program for PG-1500
Debugging Tool
IE-784000-R IE-784000-R-BK IE-784000-R-EM IE-784915-R-EM1 IE-78000-R-SV3 IE-70000-98-IF-B In-circuit emulator common to the 78K/IV Series Break board common to the 78K/IV Series Emulation board common to the 78K/IV Series Emulation board for evaluation of the PD784915 Subseries Interface adapter when using EWS as a host machine Interface adapter when using PC-9800 series (except notebook type) as a host machine Interface adapter and cable when using notebook type PC-9800 series as a host machine Interface adapter when using IBM PC/ATTM as a host machine Emulation probe common to the PD784915 subseries Conversion socket for 100-pin plastic QFP to mount a device on a target system System emulator for all 78K/IV series devices Integrated debugger for IE-784000-R Device file common to the PD784915 subseries
IE-70000-98N-IF
IE-70000-PC-IF-B EP-784915GF-R EV-9200GF-100 SM78K4 ID78K4
Note 3
Note 3 Note 4
DF784915
*
Real-time OS
RX78K/IV MX78K4
Note 4
Real-time OS common to the 78K/IV series OS common to the 78K/IV series
Note 2
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PD78P4916
Notes 1. * PC-9800 series (for MS-DOSTM) based * IBM PC/AT and compatibles (for PC DOSTM , WindowsTM , MS-DOS, and IBM DOSTM) based * HP9000 series * 700TM (for (for HP-UXTM) based SPARCstationTM SunOSTM) based
*
* NEWS TM (NEWS-OSTM) based 2. * PC-9800 series (for MS-DOS) based * IBM PC/AT and its compatibles (for PC DOS, Windows, MS-DOS, and IBM DOS) based 3. * PC-9800 series (for Windows on MS-DOS) based * IBM PC/AT and its compatibles (for PC DOS, Windows, MS-DOS, and IBM DOS) based * HP9000 series 700 (for HP-UX) based * SPARCstation (for SunOS) based 4. * PC-9800 series (for MS-DOS) based * IBM PC/AT and compatibles (for PC DOS, Windows, MS-DOS, and IBM DOS) based * HP9000 series 700 (for HP-UX) based * SPARCstation (for SunOS) based Remark The RA78K4, CC78K4, SM78K4, and ID78K4 should be used in combination with the DF784915.
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PD78P4916
*
APPENDIX B.
SOCKET DRAWING AND RECOMMENDED FOOTPRINT
Figure B-1. EV-9200GF-100 Drawing
(For reference purpose only)
A B F M N
E
O
R D C S
K
EV-9200GF-100
1
No.1 pin index
P
G H I EV-9200GF-100-G0 ITEM A B C D E F G H I J K L M N O P Q R S MILLIMETERS 24.6 21 15 18.6 4-C 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 INCHES 0.969 0.827 0.591 0.732 4-C 0.079 0.031 0.472 0.89 0.996 0.236 0.654 076 0.323 0.315 0.098 0.079 0.014
2.3 1.5
0.091 0.059
50
Q
L
J
PD78P4916
Figure B-2. Recommended EV-9200GF-100 Footprint (For reference purpose only)
G
J K
D
L
C B A EV-9200GF-100-P1 ITEM A B C D E F G H I J K L Caution MILLIMETERS 26.3 21.6 INCHES 1.035 0.85
0.650.02 x 29=18.850.05 0.026 +0.001 x 1.142=0.742+0.002 -0.002 -0.002 0.650.02 x 19=12.350.05 0.026 +0.001 x 0.748=0.486 +0.003 -0.002 -0.002 15.6 20.3 12 0.05 6 0.05 0.35 0.02 0.614 0.799 0.472 +0.003 -0.002 0.236 +0.003 -0.002 0.014 +0.001 -0.001
2.36 0.03 2.3 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
I
H
F E
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PD78P4916
*
APPENDIX C.
RELATED DOCUMENTS
Document related to device
Title Document No. Japanese English U10444E -- U10905E -- -- --
PD784915 Subseries User's Manual - Hardware PD784915 Subseries Special Function Register Table
78K/IV Series User's Manual - Instructions 78K/IV Series Instruction Table 78K/IV Series Instruction Set 78K/IV Series Application Note - Software Basics
U10444J U10976J U10905J U10594J U10595J U10095J
Development tool documents (User's Manual)
Title Document No. Japanese RA78K Series Assembler Package Language Operation RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler Language Operation CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PG-1500 Controller IE-784000-R IE-784915-R-EM1 EP-784915GF-R PC-9800 series - MS-DOS base IBM PC series - PC DOS base EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEU-777 EEU-651 EEU-704 EEU-5008 EEU-5004 U10931J U10440J English EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 -- EEU-1335 EEU-1291 U10540E EEU-1534 -- IEU-1412
ID78K4 Integrated Debugger - Reference
Embedded-software documents (User's Manual)
Title Document No. Japanese RX78K/IV Series Real-time OS Basics Installation Debugger U10604J U10603J U10364J English -- -- --
Caution The contents of the documents listed above are subject to change without prior notice to users. Be sure to use the latest edition when starting design.
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PD78P4916
Other documents
Title Document No. Japanese Semiconductor Device Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcontroller-Related Product Guide - Third Party Products IEI-635 C10535J IEI-620 IEM-5068 MEM-539 MEI-603 MEI-604 English IEI-1213 C10535E IEI-1209 -- -- MEI-1202 --
*
Caution The contents of the documents listed above are subject to change without prior notice to users. Be sure to use the latest edition when starting design.
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PD78P4916
[MEMO]
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PD78P4916
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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PD78P4916
FIP is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The application circuits and their parameters are for reference only and are not intended for use in actual design-in's.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94.11

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